1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to contact structures for nanoscale channel devices.
2. Discussion of Related Art
Advances in semiconductor devices and the ongoing quest for miniaturization of the semiconductor devices lead to a demand for better fabrication processes for ever smaller structures because smaller devices typically equate to faster switching times, which lead to increased performance.
In order to achieve this increased device performance, smaller device channel lengths are required and so many non-planar device configurations such as dual-gate, FinFET, tri-gate and omega-gate on both bulk silicon substrates and silicon on insulator (SOI) substrates have been proposed. To fabricate nanoscale transistors having an arbitrarily large drive current, device architecture can include an additional or multiple semiconductor bodies or fingers, creating multiple parallel channels. FIG. 1 is a perspective illustration of a multi-channel tri-gate transistor on silicon on insulator 102. A multi-channel transistor 100 includes a single crystalline silicon substrate 101 having an insulating layer 103, such as a buried oxide formed thereon. On the insulating layer, multiple semiconductor bodies or fingers 105 are formed as shown in FIG. 1. A gate dielectric layer 112 is formed on the multiple semiconductor bodies 105 and a gate electrode 113 formed on the gate dielectric 112, strapping across the multiple semiconductor bodies 105. Source 116 and drain 117 regions are formed in the single crystalline semiconductor layer along laterally opposite sides of gate electrode 113.
For a typical tri-gate device, each semiconductor body 105 has a gate dielectric layer 112 formed on its top surface and sidewalls as shown in FIG. 1. Gate electrode 113 is formed on and adjacent to each gate dielectric 112 on each of the semiconductor bodies 105. Each semiconductor body 105 also includes a source region 116 and a drain region 117 formed in the semiconductor body 105 on opposite sides of gate electrode 113 as shown in FIG. 1. The source regions 116 and drain regions 117 of the semiconductor bodies 105 are electrically coupled together by the semiconductor material used to form semiconductor bodies 105 to form a source landing pad 118 and a drain landing pad 119 as shown in FIG. 1. The source landing pad 118 and drain landing pad 119 are each electrically coupled though metal contact structures 123 to upper levels of interconnect metallization (e.g., metal 1, metal 2, metal 3 . . . ) used to electrically interconnect various transistors 100 together into functional circuits. As shown in FIG. 1, a pair of metal contact structures 123 is provided for each of the semiconductor bodies 105, a first metal contact structure for the source region 116 and a second metal contact for the drain region 117 in order to maintain the parallel circuit architecture of the entire transistor.
With the metal contact architecture shown in FIG. 1, as the pitch of the semiconductor bodies 105 decreases, the pitch 110 of the metal contact structures 123 must also decrease. If the reduction in pitch 110 of the metal contact structures 123 fails to keep pace with the reduction in pitch of the parallel semiconductor bodies, the total resistance of the metal contact structures, the external resistance (Rext), becomes a significant contributor to the overall parasitic resistance of the device 100. Thus, the metal contact structures 123 are constrained by the minimum photolithographic pitch of the metal contact structures 123, causing Rext to increase as the pitch of the semiconductor bodies 105 decreases below the minimum photolithographic pitch of the metal contact structures 123.